The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating layers or inter-level dielectric layers (ILDs) to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step to create multi-level, high density metal interconnections needed for advanced high performance integrated circuits. The most frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulators or ILDs by using so-called low k materials to avoid capacitance coupling between the metal interconnects. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9. One class of low-k material that have been explored are organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD.
Recently, porous low k materials have been employed in damascene processes. A void-filled, or porous dielectric material has a lower dielectric constant than the fully dense void-free version of the same material. Such porous low-dielectric constant materials may be deposited by chemical vapor deposition (CVD), or may be spun on in liquid solution and subsequently cured by heating to remove the solvent. Porous low-dielectric constant materials are advantageous in that they have a dielectric constant of 3.0 or less. Examples of such porous low-dielectric constant materials include porous SiLK™ and porous silicon carbonated oxide, as examples. A porogen may be included in the porous low-dielectric constant materials to cause the formation of the pores.
Many of the low k materials, however, have properties that are incompatible with other materials employed to fabricate semiconductor devices or are incompatible with processes employed to fabricate the semiconductor devices. For example, adhesion to layers formed from a low dielectric constant material by adjacent layers is often poor, resulting in delamination. Additionally, layers formed from low dielectric materials are often structurally compromised by Chemical Mechanical Polishing (CMP) processes through erosion, as well as adsorption of CMP slurry chemicals. Etching processes often produce micro-trenches and rough surfaces in layers formed from materials having low dielectric constants, which is often unsuitable for subsequent photolithography processes. As a result, these materials are problematic to integrate into damascene fabrication processes. To overcome some of these problems a cap or capping layer typically formed from a material such as SiO2 is employed to protect the low dielectric materials during the CMP processes. The cap layer also serves as a hardmask when the vias and trenches are etched. Unfortunately, the dielectric constant of the capping layer is generally greater than the dielectric constant of the low k material, thereby increasing the overall capacitance of the semiconductor device.
Accordingly, it would be desirable to provide a damascene interconnect structure that includes a porous low k material to reduce the structure's overall dielectric constant but which has a relatively thin capping layer so that the capacitance of the structure is not unduly increased.